
20
AT/TSC8x251G2D
4135F–8051–11/06
Configuration Byte 1
Table 13.
Address Ranges and Usage of RD#, WR# and PSEN# Signals
Notes: 1. This selection provides compatibility with the standard 80C51 hardware which has
separate external memory spaces for data and code.
RD1
RD0
P1.7
P3.7/RD#
PSEN#
WR#
External
Memory
00
A17
A16
Read signal for all
external memory
locations
Write signal for all
external memory
locations
256 KB
0
1
I/O pin
A16
Read signal for all
external memory
locations
Write signal for all
external memory
locations
128 KB
1
0
I/O pin
Read signal for all
external memory
locations
Write signal for all
external memory
locations
64 KB
1
I/O pin
Read
signal for
regions 00:
and 01:
Read signal for
regions FE: and FF:
Write signal for all
external memory
locations
2
× 64 KB(1)